1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a trench isolation structure which includes dielectric sidewall spacers having a relatively low dielectric constant arranged upon an oxide liner incorporated with nitrogen.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves forming numerous devices in active areas of a semiconductor substrate. Select devices are interconnected by conductors which extend over a dielectric that separates or "isolates" those devices. Implementing an electrical path across a monolithic integrated circuit involves selectively connecting devices which are isolated from each other. When fabricating integrated circuits, it is therefore necessary to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for a MOS integrated circuit is a technique known as the "shallow trench process". Conventional trench processes involve the steps of etching a silicon-based substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then refilling the shallow trench with a deposited dielectric. The trench dielectric is then planarized to complete formation of a trench isolation structure in field regions of the substrate. The trench isolation structure is formed during the initial stages of integrated circuit fabrication, before source and drain implants are placed in active areas of the substrate which are interposed between the field regions. Trench isolation processing serves to prevent the establishment of parasitic channels in the field regions between active areas. The trench process is becoming more popular than the local oxidation of silicon ("LOCOS") process, another well known isolation technique. The shallow trench process eliminates many of the problems associated with LOCOS, such as bird's-beak and channel-stop dopant redistribution problems. In addition, the trench isolation structure is fully recessed, offering at least a potential for a planar surface. Yet further, field-oxide thinning in narrow isolation spaces is less likely to occur when using the shallow trench process.
While the conventional trench isolation process has many advantages over LOCOS, the trench process also has several problems. Because of an increased desire to build faster and more complex integrated circuits, the semiconductor industry has devoted much effort to reducing the feature sizes of and the separation between active devices arranged within a semiconductor substrate. Consequently, the lateral width of the trench isolation structure has grown increasingly smaller. To ensure that a trench isolation structure can effectively isolate active devices, the capacitance between those active devices must be minimized. The value of this capacitance is dependent upon the lateral width of the isolation structure and the relative permittivity of the trench dielectric, which is typically silicon dioxide ("oxide"). Permittivity, .epsilon., of a material reflects the ability of the material to be polarized by an electric field. The capacitance between two active areas separated by a dielectric is directly proportional to the permittivity of the dielectric. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, .epsilon..sub.o. Hence, the relative permittivity or dielectric constant of a material is defined as:
K=.epsilon./.epsilon..sub.o.
The capacitance between active areas laterally spaced apart by a dielectric increases as the lateral width of the dielectric decreases. Unfortunately, the dielectric constant, K, of oxide is not sufficiently low (i.e., K is approximately 3.7 to 3.8) to counterbalance the effect that reducing the lateral width of the isolation structure has on the capacitance between active areas. As such, the breakdown voltage of the trench isolation structure decreases as the lateral width of the isolation structure is reduced. As a result, current may inadvertently flow between active devices separated by a narrowed trench isolation structure. In particular, current leakage between a source/drain region of one transistor and a source/drain region of another transistor may occur. In this manner, a transistor may receive a false signal, resulting in improper operation or failure of an integrated circuit employing the trench isolation structure.
Since trench formation involves etching the silicon substrate, it is believed that dangling bonds and an irregular grain structure form in the silicon substrate near the walls of the trench. In a subsequent processing step, the active areas of the semiconductor substrate may be implanted with impurity species to form source/drain regions therein. The semiconductor topography may be subjected to a high temperature anneal to activate the impurity species in the active areas and to annihilate crystalline defect damage of the substrate. Unfortunately, impurity species which have a relatively high diffusivity, such as boron, may undergo diffusion into the isolation region when subjected to high temperatures. The irregular grain structure may provide migration avenues through which the impurity species can pass from the active areas to the trench isolation structures. Moreover, the dangling bonds may provide opportune bond sites for diffusing impurity species, thereby promoting accumulation of impurity species near the edges of the isolation structures.
It is postulated that the presence of foreign atoms within a trench isolation structure may result in that structure having a relatively high defect density. For example, clusters of foreign atoms may cause dislocations to form in close proximity to the lateral edges of the trench isolation structure. It is believed that the voltage required to cause dielectric breakdown of a trench isolation structure decreases as the defect density (or doping density) within the isolation structure increases. Consequently, when a voltage is applied to a source/drain region of a transistor arranged laterally adjacent the isolation structure, dielectric breakdown may occur in those areas of the isolation structure having a high defect and/or doping density. The threshold voltage near the lateral edges of the trench isolation structure may therefore be reduced, causing current leakage within the isolation structures.
It would therefore be desirable to develop a technique for forming a trench isolation structure which would be less likely to experience breakdown during operation of an integrated circuit employing the isolation structure. It would be beneficial if the dimensions of the trench isolation structure could be reduced without being concerned with current leakage between active areas isolated by the isolation structure. Increased capacitance between active areas separated by the isolation structure could thus be prevented, despite reductions in the lateral width of the isolation structure. Reducing the doping density within the trench isolation structure would also provide better protection against dielectric breakdown of the isolation structure. An increased integration density and reduced propagation delay of active devices separated by trench isolation structures could be accomplished without sacrificing operability of the integrated circuit.